1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory, generally known as a flash memory, whose contents are electrically erasable in total or in part, and more particularly to a flash memory wherein provisions are made to ensure correct data readout despite the occurrence of over-erased memory cells.
2. Description of the Related Art
In the semiconductor memory field, vigorous development work has been under way in recent years to develop devices with cell configurations that can achieve a lower per-bit cost and that permit device miniaturization for increased memory capacity. The intention behind this is to replace magnetic storage media with semiconductor memories. At the present time, the cell structure that can achieve the goals of increased capacity and decreased cost is the one-transistor-per-cell structure having one floating gate (FG) per cell, as employed for EPROMs, and a memory generally known as a flash memory is a typical example of a memory device having such a cell structure.
A flash memory comprises a matrix array of memory cells each constructed with a transistor having a two-layered gate structure consisting of a control gate and a floating gate. Storage is achieved by utilizing the property that when prescribed voltages are applied to the control gate, drain, and source, the current flowing between the drain and source varies according to whether or not charge is stored on the floating gate. In flash memory, injecting charge into the floating gate is generally called writing.
In flash memory, reading and writing are performed by selecting a particular transistor and applying prescribed voltages to the control gate, drain, and source of the selected transistor. On the other hand, erasure is performed on one memory cell block at a time or on a plurality of memory cell blocks together, each block consisting of memory cells connected to the same common source line. Therefore, the state after erasure varies depending on variations in the characteristics of the memory cells selected for erasure and also on whether data was already written in these memory cells. In particular, if electrons are overextracted from the floating gate FG of any memory cell, the floating gate will be put in the positive state; this causes the problem of over-erasure which interferes with correct data readout because leakage current flows into the bit line connected to the memory cell even when the memory cell is in the deselect state.
Previous approaches to the elimination of such over-erasure problem have been made, for example, by reducing variations in the memory cell characteristics during manufacture, or by writing data into all the memory cells prior to erasure. Tightening up tolerances for allowable variations in the memory cell characteristics in the manufacturing process, however, introduces a problem in that the manufacturing yield decreases. Accordingly, there is a demand to provide a flash memory that can ensure correct data readout despite the occurrence of over-erased memory cells.
To reduce the effect of over-erasure, there has been proposed a configuration in which a source select transistor is added whose gate input is coupled to the same word line as the memory cell selected. In such a flash memory configuration, source lines are arranged in parallel to the word lines, one source line for every one or more than one word line, and the source lines are connected to a common source line, each via a diode and the select transistor whose control gate is connected to the word line. With this configuration, for reading, only the source line connected to the memory cell selected for reading is grounded, and the other source lines are opened. This arrangement therefore ensures correct data readout because over-erased memory cells, if connected to the same bit line, do not affect the reading.
Such a flash memory configuration, however, requires the provision of a diode via which to apply a high voltage to the source line for erasure, so that a larger spacing has to be provided between the word lines than in the structure that does not require the provision of such a diode. This not only makes it difficult to achieve a higher integration but introduces a problem in that extra steps have to be added to the wafer fabrication process in order to form such diodes.
In semiconductor memories, in order to improve the fabrication yield, redundant memory cells are included which are switched in to replace defective memory cells. The replacement of defective memory cells is usually done on a bit line or word line basis.
Such redundant design is also employed for flash memories; however, when the replacement is done on a word line basis, problems that do not occur in DRAMs and SRAMs arise in the case of flash memories since erasure is also done on a row that contains replaced defective memory cells. There can be various causes for failure. For example, when a failure is caused by a word line shorting to a source line or a device ground line, in a DRAM or SRAM such a word line should only be replaced by a redundant word line. In a flash memory, on the other hand, an erasure operation is performed by applying a high voltage to the source line in the selected source block while connecting all the word lines in the block to ground. In the case of the above failure, however, since the word lines are grounded, the memory cells connected to the replaced word line are also subjected to the same erasure conditions. However, no write operations are performed on the memory cells connected to the replaced word lines, which means that these memory cells will no doubt be put in an over-erased state after several erase operations. Since the replaced memory cells remain connected to the bit lines after the replacement, the normal memory cells cannot be read out correctly if the replaced memory cells are in an over-erased state. In other failure causes also, since the replaced memory cells are subjected to conditions close to the erasure conditions, there is a strong possibility that these memory cells will gradually be put into an over-erased state. For these reasons, in flash memories, it has not been possible to effect redundancy replacement on a word line basis.
Which of the bit line replacement or word line replacement is appropriate is usually determined in connection with the manufacturing process. In the case of flash memories, however, since the replacement cannot be done on a word line basis, redundancy replacement has always been effected on a bit line basis even in cases where the word line replacement would be more appropriate. It is therefore demanded to provide a flash memory that permits redundancy replacement on a word line basis so that the appropriate redundancy configuration can be selected.